1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device. More particularly, the invention relates to a method of manufacturing a semiconductor device by which a high voltage device and a low voltage device are simultaneously formed in such a manner that nitrification oxide films having different thickness is formed by a single oxidation process and is then nitrified to form a dual gate insulating film having an increased dielectric constant.
2. Description of the Prior Art
Two or more devices having different driving voltages are formed in a single substrate for low-power consumption and high-performance semiconductor device. In order to manufacture this semiconductor device, a dual gate oxide film in which the thickness of the gate oxide films is different depending on the devices is formed. At the same time, the thickness of the dual gate oxide film is reduced in order to implement high performance, etc. In other words, the gate oxide film of the high voltagelidevice operating at a high voltage is formed to be thicker than the gate oxide film of the low voltage device operating at a low voltage. This is for the purpose of improving the breakdown voltage characteristic against the high voltage.
The conventional method of manufacturing the semiconductor device by which the high voltage device and the low voltage device are simultaneously manufactured will be described by reference to FIG. 1A through FIG. 1C.
Referring now to FIG. 1A, a device isolation film 102 is formed at a given region of a semiconductor substrate 101, thus defining an active region and an inactive region and simultaneously defining a high voltage device region xe2x80x98Axe2x80x99 and a low voltage device region xe2x80x98Bxe2x80x99. An impurity ion implantation process for forming a well and controlling the threshold voltage is performed. A first oxide film 103 is then formed on the entire structure using hydrogen and oxygen gas. After forming a photoresist film 104 on the first oxide film 103, the photoresist film 104 is patterned to expose the low voltage device region xe2x80x98Bxe2x80x99. Then, the first oxide film 103 in the low voltage device region xe2x80x98Bxe2x80x99 is removed using fluoric acid solution by the use of the patterned photoresist film 104 as a mask, to that the semiconductor substrate 101 is exposed.
By reference to FIG. 1B, after the photoresist film 104 is removed, a second oxide film 105 having a thickness thinner than the first oxide film 103 is grown. Thereby, a dual gate oxide film consisting of the first and second oxide films 103 and 105 having different thickness is formed. A polysilicon film 106 is then formed on the entire structure including the dual gate oxide film. Thereafter, given regions of the polysilicon film 106 and the first oxide film 103 in the high voltage device region xe2x80x98Axe2x80x99 and the polysilicon film 106 and the second oxide film 105 in the low voltage device region xe2x80x98Bxe2x80x99 are selectively etched by means of a lithography process using the gate mask and an etch process, thus first and second gate electrodes. A low-concentration impurity region 107 is then formed at a given region of the semiconductor substrate 101 by means of a low-concentration impurity ion implantation process using the first and second gate electrodes as a mask.
Referring to FIG. 1C, an oxide film 108 and a nitride film 109 are formed on the entire structure. A dual spacer is then formed at the sidewalls of the first and second gate electrodes by means of a blanket etch process. Next, a high-concentration impurity ion implantation process using the first and second gate electrodes and the spacer formed at the sidewall as a mask is performed. A rapid thermal annealing (RTA) process is then performed to form a high-concentration impurity region 110 at a given region of the semiconductor substrate 101, so that a junction region is formed. Thereafter, a metal film, for example, a cobalt (Co) film is formed; on the entire structure and is then experienced by an annealing process. Due to this, the polysilicon film 106 of the metal film and the first and second gate electrodes and the semiconductor substrate 101 of the junction region react to form a salicide film 111. At this time, the salicide film 111 serves to lower the contact resistance during a wiring process. Thereafter, an insulating film is formed on the entire structure and is then flattened. A contact hole through which the gate electrode and the junction region are exposed is then formed. A conductive layer to bury the contact hole is formed and is then patterned to form a line.
As described above, the conventional method of manufacturing the semiconductor device consisting of the high voltage device and the low voltage device has the following problems.
First, the photoresist film formed on the first oxide film in the high voltage device region, made of an organic material, is not completely removed by a removal process after the first oxide film in the low voltage device region is removed. As the photoresist film may remain on the first oxide film, there is a significant problem that it may lower reliability of the gate oxide film. Also, the device isolation film is etched in the process for etching the first oxide film in the low voltage device region, there is a problem that the leakage current between the devices is increased.
Second, twice thermal oxidation processes are formed in order to grow the first and second oxide films. There is a problem that excess heat is applied to the substrate due to the twice thermal oxidation processes.
Third, the cleaning process is performed before the second oxide film is grown. This makes rough the surface roughness of the first oxide film. Thus, there is a problem that reliability of the oxide film is lowered.
Fourth, the leakage current in the gate oxide film, is greatly increased in the conventional technology wherein a thermal oxide film is used as the thickness of the oxide film is made thin. There is a physical limit in reducing the thickness of the thermal oxide film.
Fifth, when boron ions are implanted into the polysilicon film in order to manufacture a P type semiconductor device, the boron ions are penetrated into a channel region in the annealing process. Due to this, the doping concentration of the channel region is changed to vary the threshold voltage, etc. Also, in case of an N type semiconductor device, electrons and holes moving from source to drain have energy higher than the energy barrier at the interface of the semiconductor substrate and the gate oxide film due to an electric field. There is a problem that the threshold voltage, etc. is reduced since the electrons and holes are introduced into the gate oxide film.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing semiconductor device by which nitrogen ions are implanted into a given region and a dual gate insulating film is then formed by a single oxidation process.
Another object of the present invention is to provide a method of manufacturing a semiconductor device by which the dual gate insulating film formed by the single oxidation process is nitrified to increase a dielectric constant.
In the present invention, nitrogen ions having a characteristic which reduces the growth rate of an oxide film is selectively: implanted into a low voltage device region. A nitrification oxide film having a thin thickness and a nitrification oxide film having a thick thickness are then simultaneously formed by means of an oxidation process under N2O or NO ambient. The nitrification oxide film and the nitrification oxide film are then nitrified by means of a remote plasma nitrification method and are then used as a gate insulating film. Further, a dielectric constant of the nitrification oxide film is increased. A leakage current through the gate insulating film is also reduced as the thickness of an electrical gate insulating film can be reduced by increasing the physical thickness. In addition, the nitrification oxide film has a high resistance to penetration of impurities or hot carriers. Thus, penetration of boron ions of a P type device into the gate insulating film and the channel region can be prevented and the hot carrier characteristic can be improved.
In order to accomplish the above object, the method of manufacturing the semiconductor device according to the present invention, is characterized in that it comprises the steps of defining a semiconductor substrate into a high voltage device region and a low voltage device region and then forming a screen oxide film on the entire structure, performing a nitrogen ion implantation process only for the semiconductor substrate in the low voltage device region and then performing a rapid thermal annealing process, removing the screen oxide film and then performing an oxidation process under a gas ambient containing nitrogen and oxygen to form first and second nitrification oxide films having different thickness on the semiconductor substrate of the high voltage device region and the semiconductor substrate of the low voltage device region, respectively, rapidly nitrifying the first and second nitrification oxide films to form a dual gate insulating film consisting of third and fourth nitrification oxide films, forming a polysilicon film on the dual gate insulating film, etching given regions of the polysilicon film and the third nitrification oxide film in the high voltage device region and the polysilicon film and the fourth nitrification oxide film in the low voltage device region to form first and second gate electrodes, and forming a junction region at a given region of the semiconductor substrate.